The invention relates to the field of amplifier circuits, and in particular to a two-stage amplifier that can amplify both AC and DC voltage signals.
Many digital integrated circuits have been were fabricated in CMOS technology with 5-volt supply voltage. This has led to a large number of systems with a 5-volt supply on the printed circuit boards. However, as CMOS technology has developed the maximum allowable supply voltage of the digital IC""s has dropped to 3.3-volts for 0.5 xcexcm and 0.35 xcexcm technologies. In addition, it is expected that this voltage will be further reduced as newer technologies are developed. Since IC manufacturers want to use modern CMOS processes for cost reduction, a supply voltage compatibility problem results.
The publication entitled xe2x80x9cEmbedded 5 V to 3.3 V Voltage Regulator for Supplying Digital IC""s in 3.3 V CMOS Technologyxe2x80x9d, IEEE Journal of Solid-State Circuits, Volume 33, No. 7, July 1998, Page 956-962, discloses a fully integrated voltage supply in which a 5-volt supply voltage is reduced to 3.3 volts on the chip. The lower supply voltage of 3.3 volts is used to supply a CMOS digital circuit designed for lower current consumption. In an embodiment of the voltage supply, the gate connection of an n-channel output transistor is controlled by a comparator via a charge pump to create the required activation voltage. The comparator and the n-channel output transistor, which is connected as a source follower, form a two-stage amplifier with an inverting and a non-inverting input. The charge pump is a voltage doubler whose input variable is the output voltage of the comparator. Because the prevailing load on the amplifier output is not known for stability reasons, the fed-back voltage is tapped from a simulator directly from the amplifier output. A linear regulator is not used to control the voltage doubler and thus to control the amplifier, but the fed-back voltage is merely tested, in the manner of a two-point control, whether it is greater or smaller than a specified comparison value. Depending on the difference, the charge pump increases or decreases the gate voltage of the n-channel output transistor. This arrangement is not very well suited for general amplification purposes.
Therefore, there is a need for an improved two-stage amplifier that is suited for reduced supply voltages.
Briefly, according to an aspect of the invention, a two-stage amplifier includes a first stage and a second stage that are DC-connected through a coupling capacitor Cp. The first and second amplifier stages are DC isolated from one another by the coupling capacitor. A charge pump generates a bias voltage Vp that is applied across the coupling capacitor Cp. The charge pump is connected to the coupling capacitor and applies an essentially constant and floating voltage to the coupling capacitor.
Even if the first amplifier stage is a transconductance amplifier, since the output current of the first stage is effectively transferred via the coupling capacitor to the MOS input of the second amplifier stage. This applies both to DC and AC signals, as long as their frequency is less than the pump frequency. As a result, the two-stage amplifier may amplify signals with DC and AC components.
The charge pump generates a floating voltage at its outputs, in fixed proportion to a supplied reference voltage. If the first stage is a transconductance amplifier, the input of the second amplifier stage represents a dominant pole. For stability purposes, especially in the case of amplification with feedback, this dominant pole can be enlarged by a compensation capacitor. To assure DC isolation of the coupling capacitor from the charge pump, the output current paths are split by pump capacitors in an arrangement that is insensitive to stray capacitances. As a result, current can not flow through these pump capacitors from the first or second amplifier stage to ground, or to the supply connection. This allows the charge pump to operate as a voltage source as free from ground as possible. The remaining stray capacitances of the coupling capacitor and of the two pump capacitors are toward ground, and thus parallel to the compensation capacitor whose action as a pole is enhanced. The current to charge or discharge the parasitic capacitances does not need to be furnished from the first stage, but is provided by the charge pump. As a result, the current lost by the remaining stray capacitances does not result in an offset voltage at the input of the first stage.
The size of the coupling capacitor depends on the maximum output current of the first stage and the cycling rate of the charge pump. As a rule of thumb, the maximum output current of the first stage can be taken up by the coupling capacitor for the duration of a half cycle of the charge pump, without the first stage leaving the permitted output voltage range. On the other hand, the coupling capacitor should be smaller than the capacitor that forms the dominant pole at the input of the second stage. If these two considerations are no longer compatible, then the cycling frequency of the charge pump must be increased.
Charge pumps for increasing the voltage in CMOS technology are described extensively, for example, in the IEEE Journal of Solid-State Circuits, Volume 33, No. 3, March 1998, Pages 410-416, in the paper xe2x80x9cA High-Efficiency CMOS Voltage Doublerxe2x80x9d. Such circuits require a non-overlapping two-phase cycle, which increases the supply reference voltage through two pump capacitors, electronic switches, or non-linear elements. The non-overlapping two-phase cycle is generally formed in a pump generator from a supply clock signal with a pulse-pause ratio of 1:1.
These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of preferred embodiments thereof, as illustrated in the accompanying drawings.